1. Field of the Invention
The present invention relates to a semiconductor device including a lateral MOS transistor for which high driving performance is required and to a method of manufacturing it.
2. Description of the Related Art
It has become possible to manufacture small geometry MOS transistors by using a progressive fine processing technique without lowering capability. This trend also applies, without exception, to semiconductor elements, for which high driving performance is required. In order to realize the high driving performance, reduction of an ON resistance of the element per unit plane area has been attempted with the best use of a fine processing technique. However, it is also a fact that the reduction of a withstand voltage, which is caused by miniaturization of the semiconductor element, hinders further improvement of the driving performance. Semiconductor devices with various structures have been proposed in order to eliminate the trade-off between the miniaturization and the withstand voltage. A trench gate MOS transistor, which is presently a mainstream semiconductor element, is given as an example in a power MOS transistor having a high withstand voltage and high driving performance. The trench gate MOS transistor has the highest degree of integration among the MOS transistors having high withstand voltage and high driving performance. The transistor shows extremely excellent performance as a single element, but has a disadvantage in mounting on a chip with standard elements for integrated circuit since the trench gate MOS transistor has a vertical MOS structure in which current flows in a depth direction of a substrate. When coexistence with integrated circuit standard elements on a chip is taken into account, a traditional lateral MOS structure is mostly selected.
As a method capable of reducing an ON resistance per unit area of the lateral MOS transistor without lowering a withstand voltage, a lateral trench gate transistor in which a gate portion has a structure having a convex portion and a concave portion to gain a larger gate width has been proposed (for example, refer to JP 3405681 B (p. 11, FIGS. 2A to 2B)). Attached FIGS. 2A to 2D show a lateral gate transistor shown in prior art. FIG. 2A is a plan view of the MOS transistor, FIG. 2B is a sectional view taken along the line 2A–2A′, FIG. 2C is a sectional view taken along the line 2B–2B′, and FIG. 2D is a sectional view taken along the line 2C–2C′. Here, a gate electrode 003 and a gate insulating film 004 outside trenches in FIG. 2A are shown transparently in order to give underlying structure. A bold line indicates an edge of the gate electrode 003. The prior art was made to reduce the ON resistance by introducing trench structure to the gate electrode 003 to extend the gate width per unit area of a lateral MOS structure.
However, the prior art has two problems.
(1) FIG. 3 is a perspective view obtained by taking out only a source region 001 or a drain region 002 shown in FIGS. 2A to 2D. Here, the gate oxide film 004 and the gate electrode 003 are not shown. In the source region 001 or the drain region 002 shown in FIG. 3, a dark-color portion of a surface which contacts with a trench wall indicated by dotted lines is a portion 020 that contacts with a channel portion. The portion 020 that contacts with the channel portion exists on each of all the surfaces, in the source region 001 or drain region 002, which contact with the trench wall. That is, in the structures of FIGS. 2A to 2D, a contact area between the source region 001 or drain region 002 and the channel portion is determined by dimensions d1, w1, and l2. When the contact area is small, the area serves as a bottleneck as shown by current 019 shown in FIG. 4D (current density becomes dense in the source region and the drain region), which inhibits the reduction of the ON resistance. It is sufficient to extend the lengths of the dimensions d1, w1, and l2 in order to increase the contact area. First, the dimension d1 is considered. The dimension d1, which corresponds to the depth of each of the source region 001 and the drain region 002 in the case where each of the source region and the drain region is formed through normal ion implantation, is generally shallow, several thousands of Å, and there is a limit to its depth. When the dimension w1, which corresponds to the width of the concave portion of the trench, is extended without changing the width of the convex portion of the trench, the number of trenches per unit area decreases, and thus, the vertical contact area decreases. This shortens the gate width, and therefore, the dimension w1 cannot be lengthened.
As regards a method of extending the l2 as an overlap length between the source region 001 or the drain region 002 and the trench, when l2 is extended without changing the gate length, it is clear that the area increases accordingly. Further, in the case where the source region 001 and the drain region 002 are formed by self-alignment to the gate electrode 003, a method of extending l2 or a method of increasing the diffusion length of the impurities for the source region 001 and the drain region 002 is considered though, there are limitations to shortening l2. After all, there is no way but a method of extending l2 through the diffusion of the impurities. However, this method also has limitation on the length, and additionally, has a risk such as the reduction in concentration of the source region 001 or the drain region 002, which is caused by the excessive impurity diffusion. This method is, therefore difficult to be actually performed. That is, it is difficult to increase contact area in the prior art without changing the element area to reduce the ON resistance of the MOS transistor.
(2) The second problem is that there is a limitation to the trench depth. Increasing the trench width can further increase the gate width per unit area. However, this only applies to the case in a well region 005. There is a limitation to the depth of the well region 005 formed by a standard method. Thus, the trench cannot be deeper than the well region 005. If the trench is made deeper than the well region 005, current leaks to the substrate.